The application of integrated circuit manufacturing methods to produce micromachined parts and MicroElectroMechanical Systems (MEMS) has resulted in devices having a wide variety of microscopic mechanisms which are fabricated on the surface of a semiconductor wafer. Due to their size, these microscopic mechanisms are extremely vulnerable to damage from handling, small particles, moisture, air flow, and other environmental hazards. Consequently, these mechanisms are often encapsulated in a hermetically sealed package to prevent such damage.
One of the common processing steps in the fabrication of a semiconductor device is the dicing of the semiconductor wafer into individual chips which are then encapsulated in some form of package. It is desirable in many fabrication processes to encapsulate micromachined devices at the wafer level, that is, prior to separation of the wafer into individual chips. This approach is advantageous in that it avoids exposing the micromachined elements on the wafer to potential damage, either directly or through the introduction of debris, that may occur during the separation process. Wafer level encapsulation also allows the devices to be thoroughly tested in the actual encapsulated working environment of the device. This early and thorough testing, and the subsequent scrapping or reworking of defective devices, minimizes the expenditure of further processing resources on defective products.
In order for wafer level encapsulation to be feasible for a commercial scale wafer process, the encapsulation process must be compatible with commonly used die separation methods, such as wafer sawing. Ideally, the encapsulation process should also be inherently inexpensive and easy to implement. In particular, the process should allow for the use of simple, inexpensive packaging components and technologies. Many of the encapsulation technologies relied upon to date, however, are inherently complex and require the use of expensive materials.
FIG. 1 is a cross-sectional view of one type of prior art semiconductor wafer level package 21 that has been used to hermetically encapsulate a device 12. This type of device is described, for example, in commonly assigned U.S. Pat. No. 5,323,051 (Adams et al.). Typically, a plurality of such devices, together with external structures such as test devices and scribe channels, will be fabricated as part of the total semiconductor wafer level package. For the sake of clarity, however, these well known external structures have been omitted from the drawing and only the portion of the semiconductor wafer level package 21 which contains the device 12 is shown.
The device 12 of FIG. 1 is fabricated on a semiconductor substrate 11 which comprises a wafer of semiconductor material (at a later point in the fabrication process, after the device is completed and encapsulated, the wafer will be diced into a plurality of distinct chips). The device 12 may be any of the devices which are commonly fabricated on semiconductor wafers, including integrated circuit structures, micromachined sensors such as accelerometers, and other micromachined structures and MEMS devices.
A cap wafer 16 (typically ceramic) is provided which has a plurality of holes 18 extending through it. A plurality of glass walls 14 having a predetermined height and thickness are then formed on the cap wafer, and the cap wafer is bonded to the semiconductor substrate 11 by heating the cap wafer, the glass walls and the semiconductor substrate and using the glass walls as a bonding agent. In this way, the semiconductor wafer level package 21 is formed as a capped wafer structure with the device 12 hermetically sealed in a cavity 17 of predetermined dimensions formed by the semiconductor substrate, the cap wafer and the glass walls.
A plurality of metal traces 13 are fabricated on the semiconductor substrate 11 prior to formation of the glass walls 14. The metal traces form a plurality of electrodes on the semiconductor substrate which provide electrical coupling to the device 12. Since the metal traces bond firmly to the glass walls, they do not disrupt the integrity of the hermetic seal.
Prior to formation of the glass walls, holes 18 are etched in the cap wafer 16 in locations which provide ready access to a portion of the electrodes formed by the metal traces 13 that extend outside of the cavity 17. A plurality of wires 19 are bonded to a plurality of pads formed on exterior portions of metal traces. The wires extend through the holes and are themselves coupled to external electrical devices (not shown). The wires, holes and metal traces provide a plurality of electrical couplings to the device 12 while allowing the device to remain hermetically sealed within the cavity.
The two wafers are typically aligned by means of locating holes formed in each wafer into which an alignment pin is inserted during the bonding process. The capped wafer structure is then introduced into a controlled, pressurized environment which typically comprises an inert gas such as helium, argon or nitrogen. The cap wafer 16 and semiconductor substrate wafer 11 are heated in this environment to bond them together to form semiconductor wafer level package 21. The bonding hermetically seals the capped wafer structure capturing the inert gas within the cavity 17. The controlled environment provides a predetermined damping action for mechanical motion of the device 12. The predetermined damping action is readily controlled by altering the composition and pressure of the inert gas. The capped wafer structure is then diced into a plurality of composite chips by sawing, a method well known in the semiconductor art, and the composite chips are further encapsulated within a plastic material.
While the device and methodology disclosed in U.S. Pat. No. 5,323,051 (Adams et al.) represents a significant improvement in the art of hermetically sealed packages, it nonetheless has certain shortcomings. Most notably, this device generally involves the formation of a cavity which is defined by glass walls and a cap wafer. However, the formation of this cavity can be a costly and complicated process, and the formation of the walls and ceiling of the cavity directly on the wafer substrate can lead to contamination of, or damage to, the micromachined structures residing on the wafer substrate.
In some processes, the cavity in a device such as that disclosed in Adams et al. is sealed with a flat Kovar® lid. The use of Kovar® lids (which are based on Fe—Ni—Co alloys) is advantageous in that they shield the encapsulated device from RF interference. However, the use of Kovar® lids does not reduce the cost or complexity of the manufacturing process. In particular, in addition to the fabrication of the Kovar® lid itself (which typically requires electroplating, tack welding and reflow), the remainder of the cavity must still be fabricated, with the difficulties noted above.
There is thus a need in the art for a simplified and inexpensive method for encapsulating micromachined devices. There is also a need in the art for such a method which is applicable to the fabrication of packaging devices fabricated on a semiconductor wafer before the wafer is diced into individual chips, and which provides a hermetically sealed cavity within which micromachined device can move.
These and other needs are met by the structures and methodologies described herein.